1. Technical Field
The present invention relates to a test method for a ferroelectric memory and in particular to a technique for performing a stress test by applying a stress voltage to a component of a ferroelectric memory.
2. Description of Related Art
A ferroelectric random access memory (FeRAM) features nonvolatile property such as a flash memory and a high-speed read/write characteristic such as a DRAM (Dynamic Random Access Memory), which has attracted attention as a nonvolatile memory operating at high speed.
As a ferroelectric memory, JP-A-2005-209324 discloses a semiconductor integrated circuit device that includes a memory cell of a size reduced to some degree and a shared plate line and that is capable of operating at high speed by eliminating a delay caused by serial connection of memory cells.
The semiconductor integrated circuit device includes a plurality of first memory cells each including a cell transistor whose gate terminal is connected to a word line and a ferroelectric capacitor connected at one end to a source terminal of the cell transistor. The drain terminal of the cell transistor of each of the plurality of first memory cells is used as a first local bit line LBL, and the other end of each of the ferroelectric capacitors is used as a first plate line PL. A first reset transistor has a source terminal connected to the first plate line and a drain terminal connected to the first local bit line. A first block select transistor QS has a source terminal connected to the first local bit line and a drain terminal connected to the first bit line.
In a stress test for such a ferroelectric memory, stress is simultaneously applied to a plurality of memory cells so that a plurality of plate lines are driven. However, the stress test time may increase due to a delay of the rise and fall of a signal flowing through the plate line.